In memory devices, such as dynamic random access memory (DRAM), as data channel frequencies increase, maintaining signal integrity becomes more important. Thus, error correcting codes (ECCs), such as cyclical redundancy check (CRC), have been proposed for use in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device.
In a memory device, ECCs may be transmitted between a memory controller and the memory device along with command, address and data signals. The signals may be serialized into a packet and transferred along a channel. In a write command, once a packet is received by the memory device, an ECC value is calculated and compared with a known ECC value that was transmitted in the packet. If the values are the same, the command, address, and write data signals are validated and access is provided to a memory array in the memory device. Conversely, if the calculated ECC value is different from the known ECC value, then the command signal in the packet is suppressed and the write data is not sent to the memory array.
FIG. 1 shows a block diagram of a logic path 100 for calculating and comparing an ECC value in a high frequency memory device in accordance with the prior art. The logic path 100 for calculating the ECC value includes two static logic gates 102 and 106 that are clocked by respective flip flops 104 and 108. More particularly, a packet is captured by a latch 122 responsive to an input capture clock. The command signals for the write command are sent to a command decoder 110. In addition, the command signals, address signals and write data signals are sent to a set of first static logic gates (SL 1) 102. For example, if 16 bits are captured, 4 command bits would be sent to the command decoder and all 16 bits would be sent to the SL1 102. The SL1 102 completes a first part of the ECC calculation by generating a partial sum of the terms. The partial sum of the terms is output from the SL1 102, and latched into a first flip flop 104. The partial sum is output from the first flip flop 104 and provided to a second set of static logic gates (SL2) 106. The remainder of the ECC calculation is completed in the SL2 106. Moreover, the calculated ECC is compared with the transmitted ECC in the SL2 106. When the calculated ECC value matches the transmitted ECC value, the SL2 106 generates an ECC valid signal. From the SL2 106, the ECC valid signal is latched into a second flip flop 108 before being provided to an ECC valid logic gate 120.
In parallel, a command decoder 110 decodes the command signals in the packet. The decoded command signals are clocked by a first and second flip flop 114 and 118, respectively, so that the decoded command signal can be provided to the ECC valid logic gate 120 at the same time the ECC valid signal is provided to the ECC valid logic gate 120. Thus, the decoded command signals are clocked out of the second flip flop 118 at about the same time as the ECC valid signal is clocked out of the second flip flop 108. The ECC valid logic gate 120 validates the command and provides access to the memory array (not shown) when the calculated ECC value is the same as the transmitted ECC value. Conversely, the ECC valid logic gate 120 suppresses the command, when the calculated ECC value is different from the transmitted ECC value.
A timing diagram showing the delay for the logic path 100 of FIG. 1 is show in FIG. 2. In FIG. 2, at time T0 the signals on the packet that are applied to input terminals become valid. At time T1 and in response to a rising edge of the clock signal, the signals are captured and provided to the SL1 102 (FIG. 1). The partial sum of terms is output from the SL1 102 at time T2, which is some time period greater than a half period of the clock signal shown at the top of FIG. 2. At time T3 and in response to a rising edge of the clock signal, the partial sum of terms is clocked into the first flip flop 104 and provided to the SL2 106. The ECC valid signal is output from SL2 106 at time T4 and provided to the second flip flop 108, which, again, requires a time period greater than a half period of the clock signal for the SL2 106 to output the ECC valid signal. At time T5 and in response to a rising edge of the clock signal, the ECC valid signal is clocked into the second flip flop 108, and the decoded command signal is clocked out of the second flip flop 118. At time T6 the decoded command signal and ECC valid signal are provided to the ECC valid logic gate 120. The ECC valid logic gate 120 generates an array command signal at time T7. The array command signal provides access to the memory array.
It can be seen from FIG. 2 that it requires two clock periods (i.e., T1-T5) after the packet is applied to the memory device to validate the command signals in the packet. The signals from the SL1 102 cannot be clocked into the first flip flop 104 by the falling edge of the clock signal after T1 because the SL1 102 requires more than one half period to complete its calculation. For the same reason, the signals from the SL2 106 cannot be clocked into the second flip flop 108 by the falling edge of the clock signal following T3. Yet considerable time is wasted after the SL1 102 and SL2 106 complete their calculations, and the signals from the SL1 102 and the SL2 106 are clocked into the flip flops 104 and 108, respectively, at time T3 and T5, respectively.
For high frequency clock speeds, the prior art method shown in FIG. 1 for calculating ECC calculations has delay characteristics greater than one internal memory device clock cycle. When the ECC delay exceeds one clock period, a second clock period delay must be added to the delay to align the ECC calculation with the command signals to validate the command before accessing the memory array. Therefore, when the ECC logic delay is greater than one clock cycle but much less than two clock cycles, an entire second clock period delay is added.
One solution in the prior art for minimizing the delay associated with calculating and comparing the ECCs values has been to slow down the frequency of the internal memory clock cycle. By slowing down the clock frequency, the calculation and comparison of the ECC can be done in less time. In particular, the SL1 102 can complete its calculation by the falling edge following the rising edge that clocks the signals into the latch 122. Similarly, the SL2 106 can complete its calculation by the falling edge following the rising edge that clocks the signals into the first flip flop 104. As a result, the calculation and comparison can be done in one clock cycle, rather than having to extend it into two clock cycles. This is not a desirable solution, however, as it reduces the bandwidth of the memory device.
Therefore, there is a need for decreasing the logic delay associated with calculating and comparing ECCs without reducing the clock frequency.